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Leads security architecture and secure development lifecycle activities for Arm IP and SoC products. Defines Root of Trust, secure boot, key management, confidential computing, cryptographic, authentication, and encryption solutions. Owns threat modeling, security requirements, documentation, verification and validation plans, certification readiness, and SDL governance from architecture through post-silicon delivery. Coordinates audits, penetration testing, issue resolution, and security sign-off while mentoring global engineering teams.

Design and verify hardware security IP and embedded processor subsystems for SoCs. Develop test plans, UVM/SystemVerilog/Verilog and C testbenches, verification models, and test strategies. Debug failures, ensure functional coverage, and support power and performance optimization. Work with design and project management teams, improve verification methodologies, and mentor engineers. Focus areas include cryptography, key management, secure boot, hardware roots of trust, ARM architectures, multi-clock and multi-power domains, and firmware/hardware co-verification.

Develop and improve front-end ASIC/SoC build methodologies, CAD flows, and automation from RTL development through implementation handoff. Build production-quality infrastructure for RTL quality, verification, IP management, regression, and release readiness. Collaborate with engineering teams and EDA vendors to resolve bottlenecks, evaluate AI and automation technologies, and drive methodology adoption across projects.

Support deployment, training, and support of internal SoC design and verification flows. Work with project engineers and methodology developers to ensure front-end and back-end flows function correctly, ramp teams, liaise with EDA vendors to resolve tooling issues, and identify efficiency improvements across engineering projects.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define system-level interconnect strategies (topology, QoS, latency, bandwidth, power), collaborate across CPU/GPU/NPU/memory teams, drive standards adoption, own performance modeling and RTL/verification strategy, lead debug/root-cause analysis, mentor engineers, and shape roadmaps for next-generation interconnect IP to support tape-out and silicon validation.

Design and architect Security IP and SoC security subsystems. Develop RTL, constraints, and specifications; drive design exploration, optimization, and bug fixes. Collaborate with verification and implementation for test plans, verification closure, debug, and sign-off. Mentor team members and support project management, roadmaps, and processes.

Lead a global team to define and deliver SoC-level clock, reset, power and thermal architectures. Manage requirements, prototypes, verified designs, cross-functional partners and post-silicon bring-up to produce power-efficient SoC products. Drive solutions for DVFS, power gating, voltage regulation, digital clocking, resets, and standards compliance.

Design and define SoC security architectures including Root of Trust, Secure Boot, key management, confidential compute, attestation, secure manufacturing, and device lifetime management. Perform threat modeling, cryptographic and side-channel analysis, define software security requirements, and lead cross-functional teams to implement hardware/software access control, isolation, and security policies.

Senior PCIe Verification Engineer responsible for creating and executing verification plans and testbenches for PCIe IP/SoC, debugging designs, collaborating with RTL designers and validation teams, and ensuring protocol compliance and quality.

Design and integrate PCIe, CXL, UCIe and other I/O subsystems into SoCs. Write micro-architecture specs, develop RTL in Verilog, run static checks, debug builds, collaborate with verification, performance, and backend teams, and mentor others to deliver complex SoC projects.