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The Senior ASIC Verification Engineer will verify high-speed coherent interconnect designs, develop verification infrastructure, and ensure correctness of the designs while collaborating with various teams.

Design and develop high-speed mixed-signal interfaces and analog circuits for next-generation NVLINK products. Responsibilities include circuit architecture, transistor-level schematic design, layout guidance, verification, simulation, optimization, silicon characterization, and post-silicon debugging. The role requires deep-submicron CMOS and FinFET experience, analog simulation expertise, behavioral modeling, testbench development, and collaboration with layout and engineering teams.

Design and build foundational security services for NVIDIA DGX Cloud’s large-scale GPU infrastructure. Develop automated Infrastructure-as-Code and Policy-as-Code enforcement, orchestration guardrails, identity and secrets services, scanning APIs, and security response systems. Integrate security products into API-first platforms and CI/CD workflows, conduct threat modeling, and secure distributed cloud-native systems. Collaborate with infrastructure, security, and product engineering teams across omni-cloud and on-premise environments.

Verify inference accelerator ASIC designs at block and SoC levels using advanced methodologies, random stimulus, functional coverage, assertion-based verification, SystemVerilog, and UVM. Develop testbenches, verification infrastructure, reference models, and automated flows; debug designs; collaborate with architects, designers, and pre- and post-silicon teams; and improve verification productivity through innovative techniques.

As a Senior Formal Verification Engineer, you will verify ASICs using formal methods, collaborate multi-functionally, lead methodology enhancements, and mentor junior engineers while ensuring compliance and correctness.