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The Senior ASIC Verification Engineer will verify high-speed coherent interconnect designs, develop verification infrastructure, and ensure correctness of the designs while collaborating with various teams.

The engineer will develop algorithms and optimizations for NVIDIA's LPX inference stack, focusing on compiler components, performance metrics, and collaboration with hardware teams.

Develop algorithms and optimizations for LPX inference and compiler stack, focusing on deep learning and performance enhancements across NVIDIA systems.

The role involves developing verification infrastructure, executing test plans, ensuring code coverage, and collaborating with design teams for post-silicon verification.

Lead the strategy and evolution of internal hardware infrastructure tools used in ASIC development, optimize workflows, and drive cross-functional alignment to enhance engineering productivity.

The role involves developing AI and ML applications to enhance chip design, collaborating with hardware teams, and creating innovative tools for productivity.

You will verify ASIC design implementation, develop verification infrastructure, optimize verification flows, and collaborate with teams on advanced methodologies.

As a Senior Formal Verification Engineer, you will verify ASICs using formal methods, collaborate multi-functionally, lead methodology enhancements, and mentor junior engineers while ensuring compliance and correctness.

Drive AI-enabled ASIC development methodology by identifying cross-stage bottlenecks, building data pipelines and metrics, creating automation and AI models, mentoring engineers, and evaluating advances in AI and EDA to improve predictability, convergence, and cycle time.

The role involves optimizing neural reconstruction workflows using CUDA and PyTorch, analyzing GPU performance, and collaborating to ensure quality and performance improvements in 3D reconstruction systems.