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The role involves mixed-signal design engineering focusing on timing analysis, circuit design using Cadence ADE, and verification methodologies.

The Compiler Engineer will design, develop, and maintain Intel's LLVM-based compiler stack, collaborating with hardware teams and contributing to Clang and SYCL technologies, ensuring optimal compiler performance for AI and HPC applications.

Design and verify complex analog circuit layouts, perform microfloor planning and power/grid/ESD verification, troubleshoot tools and flows, and collaborate with circuit and structural teams to optimize area, power, reliability, and performance.

The Modeling Development Engineer will integrate and validate software for microcontroller firmware and silicon models, leveraging expertise in silicon design and modeling development practices.

Lead design and validation of analog circuits for high-speed SerDes applications, guiding junior engineers, and collaborating across functions. Requires extensive experience in analog/mixed-signal design.

Design and develop analog circuits for high-speed SerDes applications, optimizing performance, testing designs, and mentoring engineers. Collaborate across teams to ensure designs meet specifications and drive technical direction.

The Senior Verification Engineer will lead ASIC design verification efforts, develop verification strategies, create test plans, and mentor junior engineers while ensuring coverage compliance.

The Senior Pre-Silicon Verification Engineer will develop verification strategies for mixed-signal designs, execute plans, and collaborate with teams to ensure functional compliance before fabrication.

Lead and execute post-silicon functional validation for SerDes IP: develop validation strategies, design test plans and infrastructure, debug mixed-signal issues, perform root-cause analysis, document results, and collaborate with architecture, design, board, platform, and manufacturing teams to optimize validation and failure resolution.