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Lead the verification of Serdes systems, develop UVM/SV testbenches and test cases, and mentor junior engineers while ensuring design quality and integration.

Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.

As a Verification Engineer, you will lead the verification of Serdes by developing AMS SystemVerilog models, collaborating with the design team, and ensuring model quality.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

Lead product strategy and execution for die-level co-packaged optics, selecting and qualifying VCSELs, photodetectors, lenses, and fiber interfaces; define assembly-aware optical specs, drive optical-electrical co-design within foundry constraints, and coordinate cross-functional alignment with silicon, packaging, and marketing teams.

The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.

The Principal Digital Verification Engineer will lead technical verification of chiplet products, develop UVM-based test environments, execute verification plans, and mentor junior engineers.

As a Principal Physical Design Engineer, you will lead ASIC development from RTL to GDSII, oversee design flow optimization, and ensure the delivery of high-performance products.