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Lead a team of Senior Customer Solutions Architects and Engineers, engaging with customers and partners to deliver AI technology solutions. Focus on building a skilled team, developing customer needs understanding, and guiding technical engagements for deployment of enterprise products.

As the Lead Signal and Power-Integrity (SIPI) Engineer, you will establish best practices for SIPI analysis, drive product design improvements, and mentor junior engineers. Collaborating with cross-functional teams, you will conduct analyses and support innovative solutions for high-power electronics within Tenstorrent's chiplet-based products.

As a Staff Engineer focusing on Fabric and Memory Subsystem design for high-performance SoC, you will develop these subsystems from the ground up, collaborate with multiple teams, optimize for power and performance, evaluate IP components, and ensure high-quality RTL implementations using Verilog.

The SOC Top/Debug Implementation Engineer will lead the debug solution and architecture for a high-performance AI SOC, collaborating with cross-functional teams to implement top-level debug strategies and ensure effective post-silicon validation. Responsibilities include optimizing debug infrastructure and assisting in silicon bring-up efforts.

As a Principal Reliability Engineer at Tenstorrent, you will design and execute reliability testing plans for products, focusing on enhancements from wafer to board level. Responsibilities include building statistical models for reliability predictions, defining lifetime profiles, and ensuring adherence to industry standards in collaboration with cross-functional teams.

The Sr Staff Engineer in SoC Design and Integration will configure AI processor subsystems, develop integration tests using SystemVerilog, Python, or C/C++, manage synthesis constraints, and ensure post-synthesis validation. The role involves technical documentation and collaborating with internal teams to deliver high-quality IP for AI processors.

The Technical Program Manager will oversee and coordinate the development of various chiplets for RISC-V CPUs, managing project plans and ensuring effective communication among teams. Responsibilities include tracking program progress, conducting reviews, and managing risks associated with chiplet and SoC development.