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The Risc-V Architect will analyze AI workloads, design custom RISC-V cores, and lead the architecture efforts at Tenstorrent, improving CPU performance.

Develop and optimize low-level infrastructure software that interfaces with Tenstorrent hardware. Build libraries and APIs for inter-node communication and synchronization, improve performance and scalability in distributed environments, support hardware bring-up, testing, deployment, and integrate components with runtimes and programming models.

Lead post-silicon debug and bring-up for AI accelerator platforms, diagnosing hardware and firmware failures across chips, boards, and systems. Drive root-cause analysis for power, thermal, memory, high-speed links, PCIe and NoC issues; build debug tools, automation, and methodologies; collaborate with ASIC, firmware, and software teams to resolve complex system-level problems and improve reliability.

As a Power Architect at Tenstorrent, you'll drive architectural strategy to optimize power across AI compute systems, using advanced estimation tools and modeling techniques.

Own end-to-end physical implementation of AI accelerator and RISC-V IP blocks from synthesis through PnR, timing closure, and GDSII signoff. Drive PPA outcomes, collaborate with RTL owners, build floorplans, power grids, pin placement and clocking strategies, and deliver LEF/DEF, timing and power models, GDS, and signoff reports for tapeouts on advanced nodes.

Lead post-silicon power characterization and correlation for semiconductor products, develop measurement strategies, and improve power architectures to meet specifications.

Design, implement, and optimize low-level compute kernels for parallel ML workloads. Write high-performance C/C++ code, tune instruction-level latency, memory, and bandwidth, profile and debug a low-level software stack, and collaborate with ML and hardware engineers to integrate optimizations into production ML pipelines.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.

Design and validate high-bandwidth interconnects for AI clusters across copper and optical media. Define architectures, perform link and channel budget analysis, lead qualification and reliability testing, develop validation plans for transceivers and cables up to 1.6T, and coordinate with suppliers and manufacturing.

As Director of Customer Engineering, manage technical customer relationships, translate needs into engineering specifications, and enhance collaboration between customer teams and internal engineering.