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Verify PCIe/CXL high-speed IOs at subsystem level: create verification strategies and test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation and emulation, analyze performance and interoperability, debug issues, improve methodologies, and mentor junior engineers while collaborating with architects and project management.

Design and integrate PCIe, CXL and other subsystems for SoCs: write micro-architecture specs, develop RTL in Verilog, debug, run static checks, collaborate with verification, performance analysis and backend teams, and mentor team members.