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As an ASIC Methodology Engineer, you will enhance AI hardware development methodologies by leveraging automation and AI to improve efficiency and quality in the ASIC lifecycle.

Develop an AI Platform for efficient training and inference of large scale models, focusing on scheduling and resource management.

The role involves building AI inference systems, optimizing GPU performance, and developing benchmarking methodologies for large-scale deployments.

The Developer Relations Manager will build partnerships to support AI solutions, provide technical advisory, and collaborate with internal teams to enhance adoption of NVIDIA technologies.

The role involves developing algorithms for inference optimization, building compiler components, and collaborating across teams to enhance performance on NVIDIA platforms.

The Senior ASIC Verification Engineer will verify high-speed coherent interconnect designs, develop verification environments, and collaborate with teams to ensure correctness of designs in a technology-focused environment.

Lead deep-learning inference optimization for edge/autonomous systems: analyze models to operator/kernel level, benchmark and deploy TensorRT/compiler solutions on Jetson/DRIVE/ARM/GPU platforms, collaborate with compiler/runtime/hardware teams, and engage partners to deliver production-ready performance improvements.

Develop and maintain hardware abstraction layers, core system libraries, drivers, and runtimes; improve reliability via automation and diagnostics; debug multi-component system issues; support hardware bring-up and NPI; collaborate with hardware, compiler, and operations teams; contribute to documentation and tooling.

Verify design and implementation of GPUs, develop verification infrastructure, collaborate with architectural teams, and ensure correctness of designs in a tech-focused environment.

The Senior Memory Controller Verification Engineer will develop verification infrastructure, drive test plan execution, ensure coverage, and support post-silicon verification and debug for complex SoC designs.