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The role involves developing synthesis algorithms for RTL designs, optimizing FPGA compilation, collaborating with cross-functional teams, and enhancing EDA tools.

The role involves developing and optimizing FPGA routing algorithms, enhancing compiler performance, collaborating cross-functionally, and debugging design issues.

The engineer will develop software tools for FPGAs, focusing on modeling, optimization, and integrating AI/ML into existing workflows.

Develop and maintain HLS compiler infrastructure, implement compiler passes and code transformations, optimize C/C++ to hardware flows, research compiler techniques for AI workloads, integrate and test HLS features, debug and validate compiler outputs, and document work for knowledge sharing.

The High Level Synthesis Compiler Engineer will develop and optimize compilers, mentor engineers, and support customers in achieving design goals in FPGA design.

Join the Quartus Device Modeling organization to tackle software and hardware challenges in FPGA development, focusing on data abstraction, complex algorithms, and AI/ML integration.

Lead and grow an STA team responsible for timing closure and signoff of advanced FPGA designs. Define STA methodology and flows, drive timing analysis, debug violations, collaborate with RTL, synthesis, P&R and architecture teams, and deliver timing-driven PPA improvements and on-time closure across multiple programs.

Perform static timing analysis and timing signoff for FPGA/ASIC designs, debug and resolve timing violations, develop and validate timing constraints, collaborate with RTL/synthesis/physical design teams, and improve STA methodology and automation to optimize performance, power, and area.