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The Staff Design Verification Engineer will verify digital circuits in high-speed communication ICs, develop verification plans, and collaborate across teams for ASIC design.

Design micro-architecture for ASICs, implement low-power RTL, collaborate with verification and physical design teams, ensure product meets customer use cases.

The role involves leading the design and evaluation of analog mixed-signal circuits, collaborating with cross-functional teams, and improving project execution processes.

The Principal Timing Engineer will focus on post RTL design flow, including synthesis, timing closure, and DFT for SerDes IPs, collaborating with design teams to deliver successful solutions.