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The Senior Staff Timing Engineer will focus on post RTL design flow, including synthesis, timing closure, and DFT generation for SerDes PHY solutions. Responsibilities involve collaborating with design teams, improving methodology, and providing support for product teams pre and post silicon.

As a Senior Staff Engineer in Digital IC Design, you will design, verify, and evaluate digital circuits for high-speed communication ICs. Responsibilities include writing engineering specifications, RTL design, synthesis, and timing analysis while collaborating with cross-functional teams to ensure successful product delivery.

The Senior Staff Engineer in Design Verification is responsible for verifying and evaluating digital circuits in high-speed data communication ICs. Tasks include developing verification plans, setting up test environments, and collaborating with teams to improve design methodology for competitive SerDes IP solutions.

The Senior Principal Analog IC Designer will lead a team in designing sophisticated CMOS transceiver and SERDES products. Responsibilities include overseeing architectural investigations, circuit designs, design verification, and managing the delivery of analog IP from concept to production. The role emphasizes collaboration with layout, verification, and application teams.

The Staff Engineer for Analog IC Design will contribute to the development of high-speed and high-performance SerDes, working with various analog circuitry and providing guidance to layout engineers. Responsibilities include design, characterization, lab debugging, and supporting customer needs.

The Staff Engineer will lead the development of high-speed SerDes and Analog Mixed-Signal IPs in advanced technology nodes. Responsibilities involve designing high performance circuitry, guiding layout engineers, working on IP characterization, and providing product and customer support.