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The Principal Timing Engineer will focus on post RTL design flow, including synthesis, timing closure, and DFT for SerDes IPs, collaborating with design teams to deliver successful solutions.

The role involves leading the design and evaluation of analog mixed-signal circuits, collaborating with cross-functional teams, and improving project execution processes.

Manage a team of layout designers, oversee analog design processes, assess layouts and risks, and ensure project schedules are met.

The Senior Staff Digital Design Engineer will design and integrate high-performance wireline PHY IPs, focusing on digital design, RTL implementation, and collaboration with mixed-signal teams to deliver robust SerDes solutions.

The engineer will design, verify, and evaluate digital circuits in high-speed data communication ICs, including developing verification plans, test environments, and collaborating with multiple teams.

Lead analog IC design for CMOS transceivers, SerDes, PLLs and data converters. Drive architectural decisions, implement/verify circuits (PLL, DLL, ADC, regulators, TX/RX, CDRs), manage analog design team, coordinate layout/verification/application, perform pre-tapeout validation and lab chip bring-up using industry tools.

As a Senior Staff Engineer, you will architect and model wireline communication systems, develop DSP techniques, and lead modeling and verification efforts.

Lead executive compensation governance for a public company: manage annual calendar, prepare Compensation Committee materials and filings, build Excel models for pay decisions and scenario planning, coordinate with Legal/Finance and external advisors, support shareholder engagement, and ensure documented, compliant, scalable compensation processes.

Support the analog design team with circuit implementation for various blocks, assist in design verification, collaborate with different teams, and participate in debugging activities under senior guidance.

The Principal Mixed Signal Design Engineer designs advanced analog ICs, leads design projects, mentors junior engineers, and collaborates across teams for circuit performance validation.