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The role involves providing technical leadership in signal and power integrity for wireline and optical interface designs, including analysis, architecture definition, and silicon validation oversight.

The Principal ASIC Design Engineer will design hardware for datacenter and AI SOCs, define micro-architecture, implement RTL designs, and collaborate across teams on various technical aspects and verification.

Oversee daily facility operations across multiple sites, manage preventive maintenance, vendor coordination, and ensure safety compliance, enhancing employee experience.

The Staff Engineer will lead the development of high-speed SerDes, design IP, and support characterization and debugging efforts in analog IC design.

Lead executive compensation governance for a public company: manage annual calendar, prepare Compensation Committee materials and filings, build Excel models for pay decisions and scenario planning, coordinate with Legal/Finance and external advisors, support shareholder engagement, and ensure documented, compliant, scalable compensation processes.

The Senior Staff Digital Design Engineer will design and integrate high-performance wireline PHY IPs, focusing on digital design, RTL implementation, and collaboration with mixed-signal teams to deliver robust SerDes solutions.

Support the analog design team with circuit implementation for various blocks, assist in design verification, collaborate with different teams, and participate in debugging activities under senior guidance.

The Principal Mixed Signal Design Engineer designs advanced analog ICs, leads design projects, mentors junior engineers, and collaborates across teams for circuit performance validation.

Design and verify high-speed analog and mixed-signal circuits (PLL, DLL, ADC, SerDes, CDR, TX/RX, regulators, amplifiers). Perform SPICE/Spectre/MATLAB simulations, post-layout verification, pre-tapeout validation, lab chip bring-up and debugging, and collaborate with layout, verification, and applications teams to deliver analog IP to production.

Design and verify mixed-signal CMOS transceiver/SERDES circuits (PLLs, DLLs, ADCs, DACs, TX/RX, CDRs, regulators, amplifiers). Perform SPICE/Spectre/MATLAB-based simulations, optimize for low-power/high-speed, and conduct lab prototype testing to meet performance targets.