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The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.

As a Staff Digital Verification Engineer, develop verification plans, maintain test environments, and ensure compliance with Ethernet standards while leading junior engineers.

The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.