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Own Jenkins-based RTL quality and release-promotion pipelines across lint, CDC, RDC, synthesis, and STA. Build QoR tracking, automated quality gates, waiver management, and evidence generation. Develop LLM-driven tooling to triage violations, create annotated pull requests, check spec-to-RTL consistency, and generate documentation. The role requires strong Python, hardware-flow knowledge, CI/CD expertise, and practical LLM integration experience. It is fully onsite Monday through Friday in the Bay Area, Vancouver, or Toronto.

Lead the verification of Serdes systems, develop UVM/SV testbenches and test cases, and mentor junior engineers while ensuring design quality and integration.

Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.

As a Verification Engineer, you will lead the verification of Serdes by developing AMS SystemVerilog models, collaborating with the design team, and ensuring model quality.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

Leads DFT architecture and implementation for chiplets, PHYs, controllers, and 2.5D/3DIC systems. Develops scan, BIST, ATPG, hierarchical test access, die-to-die test, KGD screening, and customer-ready DFT collateral. Partners with digital, analog, physical design, verification, STA, and test engineering teams. Owns DFT tools, constraints, coverage, simulation, post-silicon debug, ATE pattern bring-up, and methodology development.

Lead product strategy and execution for die-level co-packaged optics, selecting and qualifying VCSELs, photodetectors, lenses, and fiber interfaces; define assembly-aware optical specs, drive optical-electrical co-design within foundry constraints, and coordinate cross-functional alignment with silicon, packaging, and marketing teams.

The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.