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Provide administrative support for daily logistics operations: manage relationships with carriers, brokers, forwarders, and 3PLs; track supplier performance; organize import/export compliance documentation; resolve freight billing discrepancies and assist with freight invoicing and AP reconciliation.

Design and validate high-bandwidth interconnects for AI clusters across copper and optical media. Define architectures, perform link and channel budget analysis, lead qualification and reliability testing, develop validation plans for transceivers and cables up to 1.6T, and coordinate with suppliers and manufacturing.

Lead reliability strategy for next-generation AI computing systems. Drive architecture-to-production reliability, perform root-cause analyses, validate advanced cooling, coordinate cross-disciplinary teams, engage manufacturing partners, and mentor engineers to improve uptime and durability.

As Director of Customer Engineering, manage technical customer relationships, translate needs into engineering specifications, and enhance collaboration between customer teams and internal engineering.

Design and optimize high-performance SoC and IP architectures for AI workloads, focusing on RTL implementation, power, performance, and area optimization.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.

Design Verification Engineer responsible for verifying Tensix IP, building reusable SystemVerilog/Python testbenches and DV infrastructure, developing constrained-random and directed tests, closing coverage, debugging RTL/testbench/workload issues, and integrating CI/CD, simulation/emulation, and containerized regression systems. Collaborates with design, firmware, compiler, and architecture teams.