Develop and improve front-end ASIC/SoC build methodologies, CAD flows, and automation from RTL development through implementation handoff. Build production-quality infrastructure for RTL quality, verification, IP management, regression, and release readiness. Collaborate with engineering teams and EDA vendors to resolve bottlenecks, evaluate AI and automation technologies, and drive methodology adoption across projects.

Support deployment, training, and support of internal SoC design and verification flows. Work with project engineers and methodology developers to ensure front-end and back-end flows function correctly, ramp teams, liaise with EDA vendors to resolve tooling issues, and identify efficiency improvements across engineering projects.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define system-level interconnect strategies (topology, QoS, latency, bandwidth, power), collaborate across CPU/GPU/NPU/memory teams, drive standards adoption, own performance modeling and RTL/verification strategy, lead debug/root-cause analysis, mentor engineers, and shape roadmaps for next-generation interconnect IP to support tape-out and silicon validation.