Leads security architecture and secure development lifecycle activities for Arm IP and SoC products. Defines Root of Trust, secure boot, key management, confidential computing, cryptographic, authentication, and encryption solutions. Owns threat modeling, security requirements, documentation, verification and validation plans, certification readiness, and SDL governance from architecture through post-silicon delivery. Coordinates audits, penetration testing, issue resolution, and security sign-off while mentoring global engineering teams.

Design and verify hardware security IP and embedded processor subsystems for SoCs. Develop test plans, UVM/SystemVerilog/Verilog and C testbenches, verification models, and test strategies. Debug failures, ensure functional coverage, and support power and performance optimization. Work with design and project management teams, improve verification methodologies, and mentor engineers. Focus areas include cryptography, key management, secure boot, hardware roots of trust, ARM architectures, multi-clock and multi-power domains, and firmware/hardware co-verification.

Develop and improve front-end ASIC/SoC build methodologies, CAD flows, and automation from RTL development through implementation handoff. Build production-quality infrastructure for RTL quality, verification, IP management, regression, and release readiness. Collaborate with engineering teams and EDA vendors to resolve bottlenecks, evaluate AI and automation technologies, and drive methodology adoption across projects.