Teams at Arm

Senior PCIe Verification Engineer responsible for creating and executing verification plans and testbenches for PCIe IP/SoC, debugging designs, collaborating with RTL designers and validation teams, and ensuring protocol compliance and quality.

Design and integrate PCIe, CXL, UCIe and other I/O subsystems into SoCs. Write micro-architecture specs, develop RTL in Verilog, run static checks, debug builds, collaborate with verification, performance, and backend teams, and mentor others to deliver complex SoC projects.

Verify PCIe/CXL high-speed IOs at subsystem level: create verification strategies and test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation and emulation, analyze performance and interoperability, debug issues, improve methodologies, and mentor junior engineers while collaborating with architects and project management.