Senior Design Verification Engineer, AI HW

Our Tensix team is transforming AI computing by building next-generation AI accelerators that challenge industry norms. As a Design Verification Engineer, you’ll help make that vision real by validating Tensix compute cores, RISC-V processors, and chiplet-based architectures that power everything from data center inference to edge and automotive AI.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in modern DV methodologies, fluent in SystemVerilog/UVM, and comfortable reasoning from microarchitecture up to system behavior.
• Either strong growth potential as an early-career DV engineer or a proven track record verifying complex IP or SoCs at leading silicon or AI hardware companies.
• Confident working with Python-based infrastructure such as cocotb, scripting, and coverage or data analysis, and using code to automate and scale verification work.
• Deeply curious about AI and ML accelerators, and interested in how tensors, data movement, and real workloads change the way verification is designed and executed.
• Motivated by seeing advanced AI hardware in real systems, from data center deployments to edge and automotive, and ready to learn new domains quickly.

What We Need

• Contribute to verification strategies for Tensix IP and subsystems, and at senior levels help shape test plans, environments, and signoff criteria from early planning through tape-out.
• Build and maintain reusable, scalable verification environments using UVM-based testbenches, agents, and scoreboards for block and subsystem-level DV, along with Python or cocotb-based infrastructure, reference models, and checkers that stress AI datapaths and control logic.
• Execute coverage-driven verification by developing constrained-random and directed tests, defining and tracking functional, code, and assertion coverage, and closing remaining gaps with intent rather than relying only on volume.
• Debug complex issues across RTL, testbench, and workloads, including corner-case functional bugs and performance problems, while working closely with architecture, design, firmware, and compiler teams.
• Work at a scope that matches your level, ranging from taking responsibility for block-level DV and ramping quickly as an earlier-career engineer to mentoring others and influencing verification methodology and quality bars as a senior or lead engineer.

What You Will Learn

• How Tenstorrent verifies AI native compute architectures, including Tensix cores, RISC-V CPUs, chiplet fabrics, and high-bandwidth memory and interconnect subsystems.
• How to combine simulation, emulation, and software-driven workloads, bringing together RTL, firmware, compilers, and real AI models to validate both behavior and performance.
• How architectural choices in dataflow, numerical precision such as BF16 or FP8 or INT8, and on-chip networks affect verification complexity, coverage strategy, and debug.
• How to raise the bar on design verification by improving methodology, automation, and cross-team practices so that each tape-out becomes more scalable, more robust, and faster to converge.