Jobs at Tenstorrent Inc.

Designs and optimizes power distribution systems for high-performance AI accelerator cards. Responsibilities include component selection, simulation, schematic and layout guidance, VRM bring-up, validation, debugging, power integrity and PDN optimization, thermal and EMI/EMC considerations, and production readiness. The role collaborates with hardware, firmware, software, thermal, mechanical, and validation teams throughout the hardware development lifecycle.

Architect and design liquid cooling infrastructure for large-scale AI training and inference clusters. Develop chassis-, rack-, and cluster-level solutions involving CDUs, telemetry, controls, leak detection, pressure testing, fluid compatibility, redundancy, and resilient operating strategies. Partner with systems, mechanical, software, facility, and cross-functional engineering teams to deliver reliable datacenter architectures for internal and external customers.

Build and lead Tenstorrent’s global supply chain operating infrastructure for hardware products. Own product certification and market readiness, Sales & Operations Planning, global RMA and customer operations, scalable processes, KPIs, dashboards, governance, and cross-functional execution. The role requires developing teams, clarifying ownership, managing ambiguity, and aligning Engineering, Product, Sales, Manufacturing, Quality, Finance, Legal, customers, test labs, and regulatory bodies to support product launches and lifecycle operations.

Leads strategic sourcing for semiconductor design infrastructure, including third-party IP licensing, EDA/CAD tools, vendor negotiations, and complex technology contracts. Develops procurement strategies balancing cost, quality, delivery, and innovation; manages multiple concurrent deals; builds executive-level vendor relationships; and translates technical requirements into sourcing recommendations for leadership. The role supports global engineering teams and AI chip company scale-up operations.

Supports corporate development and strategic deal processes, including partnerships, business development, strategic sales, pipeline and CRM management, research, briefing materials, diligence, data-room organization, and executive communications. The role coordinates multiple workstreams and supports senior leadership throughout commercial transactions in the AI hardware, semiconductor, and data center ecosystems.

Leads analysis, modeling, structuring, negotiation, and execution of strategic partnerships and commercial transactions. Builds business cases, develops relationships across the AI, semiconductor, and data center ecosystems, manages deal workstreams, and presents strategy recommendations to senior executives and external partners.

Leads end-to-end design verification for CPU, AI accelerator, and chiplet platforms. Develops SV-UVM, C/DPI, and Cocotb simulation environments; owns test plans, coverage, regressions, failure triage, and sign-off. Collaborates with architecture, design, software, and post-silicon teams, supports emulation and multi-chip verification, and mentors junior engineers. Uses AI-assisted tools to improve verification workflows and scalability.

Own global OSAT partnerships and backend semiconductor manufacturing from wafer-out through final shipment. Manage supplier relationships, negotiations, engineering builds, qualification lots, capacity, materials, production schedules, packaging, testing, yield, quality, logistics, and supply risks. Lead substrate and critical-material sourcing for advanced AI hardware while establishing KPI-driven processes and reliable data for analytics and automation. The role requires regular travel to Taiwan and other Asia-based partner sites.

Develop and debug low-level firmware for microcontrollers and SoCs, including boot, power, and reset sequences. Lead platform bring-up, validation, production improvements, and automated testing while diagnosing hardware-software issues with lab tools. Collaborate with hardware, board, and system software teams on architecture, reliability, performance, and maintainability. Contribute to design reviews, engineering standards, mentorship, and technical leadership across the firmware lifecycle.

Develop diagnostics software to validate and stress-test ASICs, boards, and AI compute systems. Collaborate with firmware, hardware, ASIC design, verification, software, and manufacturing teams to diagnose complex system-level issues using JTAG, scripts, and hardware interfaces. Lead scalable diagnostics infrastructure improvements and support pre-silicon, post-silicon, and high-volume production validation.

Develop and maintain design verification tests and infrastructure for System Management Controllers in chiplet-based, multi-chip SoCs. Create and execute test plans, develop C/C++ tests for direct DUT execution, and triage and debug hardware/software issues with design and architecture teams. The role also involves SystemVerilog, SV-UVM, Python, co-simulation, advanced interconnect standards, and AI-assisted verification tools.

Own university and early-career recruiting strategy for a site, including school selection, campus partnerships, events, sourcing, screening, interview coordination, offers, and closing. Manage intern, co-op, and new-grad hiring funnels while partnering with engineering managers to define candidate profiles and maintain hiring standards. Build new-grad recruiting processes, track funnel metrics in the ATS, and improve candidate experience and recruiting outcomes through data-driven decisions.

Lead manufacturing cost accounting including inventory, fixed assets, and COGS. Build and scale standard costing, cost roll-ups, and controls for IPO readiness. Analyze manufacturing variances, partner with Supply Chain, Sales, and R&D, and deliver COGS and margin reporting to leadership.

Lead and scale global IT: own enterprise systems, infrastructure, security partnerships, end-user experience, and IT operations. Drive strategy, roadmaps for business applications, integrations, automation, and internal service delivery while partnering with cross-functional leaders to support rapid AI hardware and software growth.

Own multi-layer PCB layouts for high-performance AI and computing products. Route high-speed interfaces (GDDR/LPDDR/DDR, PCIe Gen5/6, Ethernet, USB), apply layout rules, select advanced fabrication (HDI, blind/buried vias, back drilling, VIPPO), collaborate with power, SI, and mechanical teams, and resolve DFM/DFA/DFT feedback to meet manufacturability and regulatory standards.

The Risc-V Architect will analyze AI workloads, design custom RISC-V cores, and lead the architecture efforts at Tenstorrent, improving CPU performance.

Develop and optimize low-level infrastructure software that interfaces with Tenstorrent hardware. Build libraries and APIs for inter-node communication and synchronization, improve performance and scalability in distributed environments, support hardware bring-up, testing, deployment, and integrate components with runtimes and programming models.

Lead post-silicon debug and bring-up for AI accelerator platforms, diagnosing hardware and firmware failures across chips, boards, and systems. Drive root-cause analysis for power, thermal, memory, high-speed links, PCIe and NoC issues; build debug tools, automation, and methodologies; collaborate with ASIC, firmware, and software teams to resolve complex system-level problems and improve reliability.

As a Power Architect at Tenstorrent, you'll drive architectural strategy to optimize power across AI compute systems, using advanced estimation tools and modeling techniques.

Own end-to-end physical implementation of AI accelerator and RISC-V IP blocks from synthesis through PnR, timing closure, and GDSII signoff. Drive PPA outcomes, collaborate with RTL owners, build floorplans, power grids, pin placement and clocking strategies, and deliver LEF/DEF, timing and power models, GDS, and signoff reports for tapeouts on advanced nodes.