Jobs at Tenstorrent Inc.

Own global compensation cycles, review processes, offer governance, and compensation data. Run end-to-end benchmarking, equity budgeting, and dilution analysis. Build SQL-based analyses and Tableau dashboards with measurable adoption. Serve as the go-to partner for HRBPs, managers, and recruiters to translate data into actionable compensation decisions.

Lead post-silicon debug and bring-up for AI accelerator platforms, diagnosing hardware and firmware failures across chips, boards, and systems. Drive root-cause analysis for power, thermal, memory, high-speed links, PCIe and NoC issues; build debug tools, automation, and methodologies; collaborate with ASIC, firmware, and software teams to resolve complex system-level problems and improve reliability.

As an AI Performance Architect, you will analyze and optimize AI workloads on Tensix architecture, linking architecture with software and hardware to enhance efficiency and scalability.

The role involves creating reference drivers for AI-IP, collaborating with teams, optimizing performance, and supporting customer-specific systems in a hybrid work environment.

As a Power Architect at Tenstorrent, you'll drive architectural strategy to optimize power across AI compute systems, using advanced estimation tools and modeling techniques.

Own end-to-end physical implementation of AI accelerator and RISC-V IP blocks from synthesis through PnR, timing closure, and GDSII signoff. Drive PPA outcomes, collaborate with RTL owners, build floorplans, power grids, pin placement and clocking strategies, and deliver LEF/DEF, timing and power models, GDS, and signoff reports for tapeouts on advanced nodes.

Lead sustainment and ramp-to-production for custom ASIC and AI hardware. Coordinate engineering, supply chain, and manufacturing partners to assure BOM readiness, material availability, process qualification, post-ramp qualification, yield and supply health. Drive risk mitigation, use ERP/PLM and project management tools, and ensure cross-functional alignment to meet schedule, quality, and cost targets.

Develop and optimize software for IP customers, including firmware, drivers, and APIs. Collaborate with cross-functional teams for software integration and troubleshooting.

Lead R&D on LLM training and inference optimization, train and evaluate large-scale models on Tenstorrent hardware, improve performance via techniques like speculative decoding, quantization, kernel fusion, flash attention and distributed training, diagnose system bottlenecks, and translate research into scalable production solutions through cross-functional collaboration.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

Design, implement, and maintain TT-Fabric, a low-level high-performance networking library for large-scale AI clusters. Build scalable communication protocols, optimize synchronization and data movement for thousands of processors, integrate APIs with AI and hardware teams, and help define the distributed systems architecture to maximize hardware performance.

As a Senior Software Engineer at Tenstorrent, you will develop AI compiler technologies, optimize computational graphs, and enhance MLIR frameworks to connect AI models with hardware.

Lead post-silicon power characterization and correlation for semiconductor products, develop measurement strategies, and improve power architectures to meet specifications.

Senior-level program manager and chief of staff supporting the CVP of Operations. Own and drive high-priority cross-functional programs from kickoff through execution, establish operating cadences, align teams on priorities, prepare leadership materials, integrate sales & operations, headcount and infrastructure planning, surface risks, and remove execution blockers to ensure organizational KPIs and milestones are met.

Build and operate AI inference deployments, write production code, debug full inference stack, collaborate with customers and engineering, and drive performance/observability improvements using Kubernetes, Helm, and LLM serving tools.

Design, implement, and optimize low-level compute kernels for parallel ML workloads. Write high-performance C/C++ code, tune instruction-level latency, memory, and bandwidth, profile and debug a low-level software stack, and collaborate with ML and hardware engineers to integrate optimizations into production ML pipelines.

Perform post-silicon power characterization and correlation for AI SoCs: develop and run power measurement strategies in the lab, analyze results vs pre-silicon models, support debug with architecture and validation teams, extend automation and scripts, and produce end-to-end power correlation reports and recommendations.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.

Provide administrative support for daily logistics operations: manage relationships with carriers, brokers, forwarders, and 3PLs; track supplier performance; organize import/export compliance documentation; resolve freight billing discrepancies and assist with freight invoicing and AP reconciliation.

Design and validate high-bandwidth interconnects for AI clusters across copper and optical media. Define architectures, perform link and channel budget analysis, lead qualification and reliability testing, develop validation plans for transceivers and cables up to 1.6T, and coordinate with suppliers and manufacturing.