Performs RTL-to-physical-design synthesis activities for ASICs, including RTL synthesis, SDC constraint development and validation, static timing analysis, script creation and modification, synthesis and STA debugging, and clean netlist generation. Requires extensive multi-node design experience and proficiency with major EDA tools including Design Compiler, PrimeTime, Tempus, and Genus.
- Job Title : Design Engineer
- Client: Arrow Electronics
- Work Location: Bay Area ,CA, onsite
- Visa: All visa, except H1B transfer
- C2C engagements are allowed.
RTL to Physical Design (RTL2PD) stage experience
RTL2PD Design Engineer(ASIC)
MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis
What candidate will Be Doing:
- RTL Synthesis, Constraint writing, validation, Static timing Analysis
- Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA
- Debug synthesis issues and STA
- Generate clean netlist.
What we are looking for:
- Experience: 8–12 years of hands-on RTL Synthesis
- EDA exposure: Design compiler, PrimeTime, Tempus, Genus,
- Multi-Node Design: Experience working with 16nm, 7nm… etc nodes.
Similar Jobs
Hardware • Manufacturing
Design, integrate, and sign off synthesizable RTL for ultra-low-power SoC blocks, including compute fabric interconnects, memory interfaces, peripherals, low-power logic, and power-management systems. Own front-end quality through lint, CDC/RDC, LEC, synthesis, timing, and power analysis. Support verification, gate-level debugging, physical-design closure, tapeout, and silicon bring-up while collaborating with architecture, DV, physical design, and firmware teams.
Top Skills:
AhbApbAtpgAxiCdcDftGate-Level SimulationI2CI2SLecLintMramNocNvmPerlPythonRdcRisc-VRramRtlRtl SimulationScan InsertionSdcSramStaSynthesisSystemverilogTclTilelinkUpfWaveform Debugging
Hardware • Manufacturing
Lead microarchitecture definition and synthesis-ready RTL implementation for processor and accelerator SoCs. Own dataflow execution fabrics, memory subsystems, on-chip networks, low-power logic, peripheral integration, and hardware/software execution models. Drive PPA optimization, verification collaboration, design documentation, mentoring, synthesis and timing closure, DFT support, tape-out, and silicon bring-up for highly energy-efficient edge-computing hardware.
Top Skills:
AhbApbAxiEccFormal VerificationI2CI2SIec 61508Iso 26262Memory Compiler ToolchainsMramNocNvmOnnxRisc-VRramRtlSdcSramStaSystemverilogTcmTfliteTilelinkUpf
27 Minutes Ago
Blockchain • Fintech • Mobile • Payments • Software • Financial Services
Graduate research interns will own end-to-end projects developing customer world models and proactive intelligence. Work spans representation learning, foundation models, reinforcement learning, agentic decision systems, and evaluation. Tasks include designing methods, running experiments, publishing findings, and potentially shipping models into production to impact customer-facing products.
Top Skills:
Deep LearningFoundation ModelsJaxPythonPyTorchReinforcement Learning
What you need to know about the Toronto Tech Scene
Although home to some of the biggest names in tech, including Google, Microsoft and Amazon, Toronto has established itself as one of the largest startup ecosystems in the world. And with over 2,000 startups — more than 30 percent of the country's total startups — Toronto continues to attract new businesses. Be it helping entrepreneurs manage their finances, simplifying business operations by automating payroll or assisting pharmaceutical companies in launching new drugs, the city's tech scene is just getting started.
