Manager, FPGA Synthesis

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams play a critical role in enabling customers to efficiently translate high-level designs into optimized hardware implementations.

Position Overview

Altera is seeking a Manager, FPGA Synthesis to lead a team responsible for developing and optimizing synthesis technology within the FPGA compiler flow. This role will drive the translation of RTL designs into efficient gate-level implementations, directly impacting performance, power, and area (PPA) across next-generation FPGA platforms.

The ideal candidate brings deep expertise in synthesis algorithms and RTL optimization, combined with strong leadership experience and a proven ability to deliver complex EDA solutions at scale.

Key Responsibilities

• Team Leadership:
  Build, manage, and mentor a high-performing synthesis engineering team; drive technical excellence, team growth, and execution.

• Synthesis Development:
  Lead the development and optimization of synthesis algorithms, including logic optimization, mapping, and netlist generation.

• Compiler Flow Ownership:
  Own and enhance synthesis stages within the FPGA compiler, ensuring seamless integration with placement, routing, and timing (STA) flows.

• QoR Optimization:
  Drive improvements in performance, power, and area (PPA) through synthesis-driven optimizations and advanced transformations.

• RTL-to-Gates Transformation:
  Guide efforts in translating high-level RTL (Verilog/SystemVerilog/VHDL) into optimized gate-level representations.

• Cross-Functional Collaboration:
  Partner with architecture, placement, routing, and timing teams to align synthesis strategies with FPGA architecture and design goals.

• Debug & Analysis:
  Oversee debugging of synthesis-related issues, including timing bottlenecks, logic inefficiencies, and mapping challenges.

• Methodology & Tool Innovation:
  Develop and implement scalable synthesis methodologies, tools, and automation frameworks.

Required Qualifications

• Experience:
  10+ years of experience in FPGA/ASIC design tools, with strong emphasis on synthesis or logic optimization
   

• Leadership:
  5+ years of experience managing or leading engineering teams
   

• Technical Expertise:

  • Deep understanding of logic synthesis, optimization techniques, and mapping algorithms

  • Strong knowledge of RTL design (Verilog/SystemVerilog/VHDL)

  • Familiarity with timing-driven synthesis and optimization (timing closure awareness)

  • Proficiency in C/C++ and software engineering best practices
     

• EDA / CAD Knowledge:
  Experience with:

  • Synthesis flows and tools (commercial or in-house)

  • FPGA or ASIC design methodologies

  • Integration with downstream flows (placement, routing, STA)
     

• Problem Solving:
  Proven ability to lead complex technical initiatives and deliver scalable, high-performance solutions
   

• Education:
  Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. Candidates with a PhD are encouraged to apply; in accordance with Canadian hiring practices, relevant experience gained during doctoral studies may be considered toward the required years of experience.

Preferred Qualifications

• Experience with FPGA toolchains (e.g., Quartus, Vivado)

• Understanding of FPGA architectures (LUTs, DSPs, BRAM, routing resources)

• Experience with advanced optimizations (e.g., retiming, resource sharing, logic restructuring)

• Familiarity with scripting (e.g., Python, Tcl) for automation

• Background in large-scale, distributed EDA development environments

Why Join Altera

• Lead synthesis development for next-generation FPGA compiler technology

• Drive innovations that directly impact performance and usability of FPGA platforms

• Collaborate with world-class teams across silicon, architecture, and software