The role involves leading the design and optimization of HLS compiler infrastructure, collaborating with teams to improve synthesis quality and performance, and mentoring junior members.

The FPGA Development Tools Engineer develops and optimizes FPGA design tools, frameworks, and benchmarks, performs analysis, and collaborates with teams to improve benchmarking methodologies.

The engineer will develop software tools for FPGAs, focusing on modeling, optimization, and integrating AI/ML into existing workflows.

The Machine Learning Engineer will develop and optimize ML models for FPGA Compiler, collaborate with engineers, and enhance compiler performance using advanced ML technologies.

Architect and develop software innovations for Quartus, focusing on optimization algorithms for FPGA tools, enhancing routing and retiming capabilities.

Join the Quartus Device Modeling organization to tackle software and hardware challenges in FPGA development, focusing on data abstraction, complex algorithms, and AI/ML integration.

Lead a team in developing and optimizing the timing analysis engine for FPGA designs, ensuring high performance and efficiency. Foster software quality and enhance user experience for Quartus tool.

As an IP Design Engineer, you will develop and verify NoC IP cores, focus on architecture, design, implementation, and customer support, while collaborating with a team to address challenges in design and integration.

The Office Administrator manages daily operations, coordinates recruitment, handles office services, budget tracking, and supports internal communications and events within the Toronto office.