The role involves designing hardware and software for ML inference IP and compilers, focusing on FPGA development and optimizing performance.

The role involves leading the design and optimization of HLS compiler infrastructure, collaborating with teams to improve synthesis quality and performance, and mentoring junior members.

Seeking a Sr Silicon Design Verification Engineer to perform functional logic verification, develop verification plans, and debug issues in pre-silicon environments, collaborating with various teams.

The FPGA Development Tools Engineer will develop algorithms and models for FPGA timing and device mapping, optimizing for performance and working closely with hardware teams.

The FPGA Development Tools Engineer will develop HLS compiler infrastructure, optimize high-level code for hardware, improve compilation flow, and implement code transformations.

Architect and develop software innovations for Quartus, focusing on optimization algorithms for FPGA tools, enhancing routing and retiming capabilities.

Develop software for Quartus compiler, enhancing FPGA support, optimizing synthesis, facilitating interactions with customers, debugging, and implementing features.

Lead a team in developing and optimizing the timing analysis engine for FPGA designs, ensuring high performance and efficiency. Foster software quality and enhance user experience for Quartus tool.

Develop and lead optimization algorithms for FPGA software, focusing on enhancing performance and efficiency in Quartus tool. Ideal candidates demonstrate research expertise and collaborative skills.