Jobs at Altera (altera.com)

Develop and verify firmware algorithms for DDR5/LPDDR5 memory calibration on FPGA IP cores. Design architecture per protocol specs, implement firmware, integrate with CAD tools, perform verification, hardware bring-up, product release support, and provide customer technical support.

The High Level Synthesis Compiler Engineer will develop and optimize compilers, mentor engineers, and support customers in achieving design goals in FPGA design.

Develop and maintain HLS compiler infrastructure, implement compiler passes and code transformations, optimize C/C++ to hardware flows, research compiler techniques for AI workloads, integrate and test HLS features, debug and validate compiler outputs, and document work for knowledge sharing.

Develop and optimize FPGA placement algorithms within the compiler toolchain to improve timing, congestion, and resource utilization. Integrate placement capabilities with routing, synthesis, and timing teams, analyze placement quality and bottlenecks, and enhance performance, scalability, and QoR for large designs.

Perform static timing analysis and timing signoff for FPGA/ASIC designs, debug and resolve timing violations, develop and validate timing constraints, collaborate with RTL/synthesis/physical design teams, and improve STA methodology and automation to optimize performance, power, and area.