The Office Administrator manages daily operations, coordinates recruitment, handles office services, budget tracking, and supports internal communications and events within the Toronto office.

The role involves leading the design and optimization of HLS compiler infrastructure, collaborating with teams to improve synthesis quality and performance, and mentoring junior members.

As an FPGA IP Software Design Engineer, you will architect, implement, and verify IP cores, develop RTL models, and support product rollouts, collaborating with various engineering teams.

The Machine Learning Engineer will develop and optimize ML models for FPGA Compiler, collaborate with engineers, and enhance compiler performance using advanced ML technologies.

Architect and develop software innovations for Quartus, focusing on optimization algorithms for FPGA tools, enhancing routing and retiming capabilities.

Lead a team in developing and optimizing the timing analysis engine for FPGA designs, ensuring high performance and efficiency. Foster software quality and enhance user experience for Quartus tool.

Develop and lead optimization algorithms for FPGA software, focusing on enhancing performance and efficiency in Quartus tool. Ideal candidates demonstrate research expertise and collaborative skills.