Teams at Altera (altera.com)

Perform static timing analysis and timing signoff for FPGA/ASIC designs, debug and resolve timing violations, develop and validate timing constraints, collaborate with RTL/synthesis/physical design teams, and improve STA methodology and automation to optimize performance, power, and area.

Lead and grow an STA team responsible for timing closure and signoff of advanced FPGA designs. Define STA methodology and flows, drive timing analysis, debug violations, collaborate with RTL, synthesis, P&R and architecture teams, and deliver timing-driven PPA improvements and on-time closure across multiple programs.

The engineer will develop software tools for FPGAs, focusing on modeling, optimization, and integrating AI/ML into existing workflows.