About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Your Team, Your Impact
Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.
What You Can Expect
What You Can Expect
- Lead a team of full-time and contract senior layout designers.
- Assess schedules, floor plans, and risks for digital macros.
- Perform hands-on work at the macro level layout.
- Manage and track layout schedules; hire additional designers as needed.
- Assess risks and plan workarounds to meet or exceed layout schedules.
- Identify and prioritize project tasks and risks.
- Work with CAD, tech, and circuit design teams to synchronize layout schedules with overall project plans.
- Understand complex layout design concepts and communicate issues cross-functionally.
What We're Looking For
What We're Looking For
- Minimum 10+ years in analog layout design and 3+ years in management.
- Deep understanding of layout methodology from initial chip planning to tape-out.
- Experience with advanced process technology and FinFET is preferable.
- High proficiency in LVS, DRC debugging, and interpreting CALIBRE DRC, ERC, LVS reports.
- Proficient in Synopsys or CADENCE layout entry tools; programming skills in Skill, Ample, or Perl are a plus.
- Strong technical and analytical background with excellent problem-solving skills.
- Excellent verbal and written communication skills; experience in conflict resolution and consensus building.
- Proven ability to build and develop a world-class analog layout team; proactive, self-starter with strong organizational skills.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
#LI-TD1
