As a DFT Engineer, you will define and implement DFT strategies, handle ATPG operations, generate JTAG interfaces, and prepare vectors for testing. Collaboration with cross-functional teams will be crucial to develop and report on DFT coverage for chiplet systems.
Join the leading chiplet startup! As an Eliyan DFT Engineer, you will be working at a fast paced early stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be defining and implementing scan, BIST, 1149, and reporting coverage. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities
- Define DFT strategy, methodologies, and implementation plan
- Implement DFT features in RTL for digital and analog blocks
- Run ATPG and create and simulate DFT vectors
- Generate TAP/JTAG interface
- Work with Analog/Mixed Signal (AMS) teams to ensure DFT support
- Work with circuit architects on boundary scan and loopback capabilities
- Prepare vectors for post-silicon
- Report status of DFT test coverage and holes
Minimum Qualifications
- General knowledge of digital and AMS circuit design techniques
- Broad knowledge of DFT methodologies and tools
- Proficient in Verilog/System Verilog and scripting
- Ability to work collaboratively with cross functional team
- Prepare test vectors and collateral for ATE test team
- BS EE or equivalent, with 2+ years of experience
Ideal Qualifications
- Breadth of expertise in MBIST, JTAG, IEEE1500, 1149, 1687, 1838
- Provide balanced tradeoffs of test time vs complexity vs coverage
- Ability to create DFT collateral for IP
- Experience with Siemens Tessent flow
- MS/PhD EE or equivalent, with 3+ years of experience
Top Skills
System Verilog
Verilog
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