Teams at Marvell Technology

The Senior Staff Digital Design Engineer will design and integrate high-performance wireline PHY IPs, focusing on digital design, RTL implementation, and collaboration with mixed-signal teams to deliver robust SerDes solutions.

Lead analog IC design for CMOS transceivers, SerDes, PLLs and data converters. Drive architectural decisions, implement/verify circuits (PLL, DLL, ADC, regulators, TX/RX, CDRs), manage analog design team, coordinate layout/verification/application, perform pre-tapeout validation and lab chip bring-up using industry tools.

The engineer will design, verify, and evaluate digital circuits in high-speed data communication ICs, including developing verification plans, test environments, and collaborating with multiple teams.