Teams at Marvell Technology

Manage a team of layout designers, oversee analog design processes, assess layouts and risks, and ensure project schedules are met.

Collaborate on high-quality analog circuit layout, using Cadence Virtuoso for simulations and verifications, ensuring optimal performance and specifications.

Contribute to chip architectures, lead micro-architecture and RTL development, and mentor junior members while working on advanced AI/HPC SOC programs.