Jobs at Marvell Technology

As a Senior Staff Engineer, you will architect and model wireline communication systems, develop DSP techniques, and lead modeling and verification efforts.

Lead executive compensation governance for a public company: manage annual calendar, prepare Compensation Committee materials and filings, build Excel models for pay decisions and scenario planning, coordinate with Legal/Finance and external advisors, support shareholder engagement, and ensure documented, compliant, scalable compensation processes.

Support the analog design team with circuit implementation for various blocks, assist in design verification, collaborate with different teams, and participate in debugging activities under senior guidance.

The Principal Mixed Signal Design Engineer designs advanced analog ICs, leads design projects, mentors junior engineers, and collaborates across teams for circuit performance validation.

Design and verify high-speed analog and mixed-signal circuits (PLL, DLL, ADC, SerDes, CDR, TX/RX, regulators, amplifiers). Perform SPICE/Spectre/MATLAB simulations, post-layout verification, pre-tapeout validation, lab chip bring-up and debugging, and collaborate with layout, verification, and applications teams to deliver analog IP to production.

Serve as primary HR leader for Marvell's GTA sites, partnering with leaders on workforce planning, employee relations, compliance, onboarding, training, investigations, engagement, and HR operations to align people strategies with business goals.

The Senior Staff Engineer will design and validate high-performance RF/Analog circuits, specifically Transimpedance Amplifiers and various analog circuits, collaborating across teams to ensure successful production.

Responsible for the design and validation of FET and BiCMOS circuits for high-speed broadband ICs and optical interface chips. Collaborate on post-silicon validation and transition to mass production.

As an Analog Layout Staff Engineer, you'll run simulations, collaborate on designs, and lead in the development of precision analog circuits, ensuring projects meet specifications through teamwork and iterative debugging.

The Sr. Staff Engineer will verify AI/HPC systems, develop test strategies, and create complex verification environments, collaborating on SoC methodologies.

The Staff Design Verification Engineer will verify digital circuits in high-speed communication ICs, develop verification plans, and collaborate across teams for ASIC design.

As a Senior Staff Engineer, you will enhance digital design flows for high-performance SerDes IP, optimize automation frameworks, collaborate on IP development, and support EDA integration, all while leveraging AI/ML techniques in a Linux environment.

The Principal Timing Engineer will focus on post RTL design flow, including synthesis, timing closure, and DFT for SerDes IPs, collaborating with design teams to deliver successful solutions.

The role involves leading the design and evaluation of analog mixed-signal circuits, collaborating with cross-functional teams, and improving project execution processes.

Collaborate on high-quality analog circuit layout, using Cadence Virtuoso for simulations and verifications, ensuring optimal performance and specifications.

Manage a team of layout designers, oversee analog design processes, assess layouts and risks, and ensure project schedules are met.

The Senior Staff Digital Design Engineer will design and integrate high-performance wireline PHY IPs, focusing on digital design, RTL implementation, and collaboration with mixed-signal teams to deliver robust SerDes solutions.

Lead analog IC design for CMOS transceivers, SerDes, PLLs and data converters. Drive architectural decisions, implement/verify circuits (PLL, DLL, ADC, regulators, TX/RX, CDRs), manage analog design team, coordinate layout/verification/application, perform pre-tapeout validation and lab chip bring-up using industry tools.

The engineer will design, verify, and evaluate digital circuits in high-speed data communication ICs, including developing verification plans, test environments, and collaborating with multiple teams.