Jobs at Marvell Technology

Design micro-architecture for ASICs, implement low-power RTL, collaborate with verification and physical design teams, ensure product meets customer use cases.

The role involves leading the design and evaluation of analog mixed-signal circuits, collaborating with cross-functional teams, and improving project execution processes.

The Principal Timing Engineer will focus on post RTL design flow, including synthesis, timing closure, and DFT for SerDes IPs, collaborating with design teams to deliver successful solutions.

The Senior Staff Digital Design Engineer will design and integrate high-performance wireline PHY IPs, focusing on digital design, RTL implementation, and collaboration with mixed-signal teams to deliver robust SerDes solutions.

As a Senior Staff Engineer, you will architect and model wireline communication systems, develop DSP techniques, and lead modeling and verification efforts.

Lead executive compensation governance for a public company: manage annual calendar, prepare Compensation Committee materials and filings, build Excel models for pay decisions and scenario planning, coordinate with Legal/Finance and external advisors, support shareholder engagement, and ensure documented, compliant, scalable compensation processes.

Oversee daily facility operations across multiple sites, manage preventive maintenance, vendor coordination, and ensure safety compliance, enhancing employee experience.

Support the analog design team with circuit implementation for various blocks, assist in design verification, collaborate with different teams, and participate in debugging activities under senior guidance.

The Principal Mixed Signal Design Engineer designs advanced analog ICs, leads design projects, mentors junior engineers, and collaborates across teams for circuit performance validation.

Design and verify mixed-signal CMOS transceiver/SERDES circuits (PLLs, DLLs, ADCs, DACs, TX/RX, CDRs, regulators, amplifiers). Perform SPICE/Spectre/MATLAB-based simulations, optimize for low-power/high-speed, and conduct lab prototype testing to meet performance targets.

Design and verify high-speed analog and mixed-signal circuits (PLL, DLL, ADC, SerDes, CDR, TX/RX, regulators, amplifiers). Perform SPICE/Spectre/MATLAB simulations, post-layout verification, pre-tapeout validation, lab chip bring-up and debugging, and collaborate with layout, verification, and applications teams to deliver analog IP to production.

Responsible for the design and validation of FET and BiCMOS circuits for high-speed broadband ICs and optical interface chips. Collaborate on post-silicon validation and transition to mass production.

The role involves leading SerDes development for high-performance analog mixed signal designs, primarily focusing on advanced technology nodes and collaborating with design teams and layout engineers.

The Senior Staff Engineer will design and validate high-performance RF/Analog circuits, specifically Transimpedance Amplifiers and various analog circuits, collaborating across teams to ensure successful production.

As a Senior Staff Engineer in Analog Layout, you will run simulations, collaborate across global teams, and deliver analog circuits through the full development cycle, ensuring high standards and effective communication.

The Staff Firmware Engineer will design, implement, and optimize SSD firmware features, perform failure analysis, and collaborate across teams to ensure effective firmware development and deployment.

Lead verification of AI/HPC SoCs, develop verification architecture using System Verilog and UVM, and analyze designs for test strategies.

As an Analog Layout Staff Engineer, you'll run simulations, collaborate on designs, and lead in the development of precision analog circuits, ensuring projects meet specifications through teamwork and iterative debugging.

Lead micro-architecture and RTL development, collaborate with teams on ASIC design, and mentor junior members for CXL products.

The Staff Design Verification Engineer will verify digital circuits in high-speed communication ICs, develop verification plans, and collaborate across teams for ASIC design.