Jobs at Marvell Technology

Manage a team of layout designers, oversee analog design processes, assess layouts and risks, and ensure project schedules are met.

Collaborate on high-quality analog circuit layout, using Cadence Virtuoso for simulations and verifications, ensuring optimal performance and specifications.

Contribute to chip architectures, lead micro-architecture and RTL development, and mentor junior members while working on advanced AI/HPC SOC programs.

The Senior Staff Digital Design Engineer will design and integrate high-performance wireline PHY IPs, focusing on digital design, RTL implementation, and collaboration with mixed-signal teams to deliver robust SerDes solutions.

The engineer will design, verify, and evaluate digital circuits in high-speed data communication ICs, including developing verification plans, test environments, and collaborating with multiple teams.

As a Senior Staff Engineer, you will architect and model wireline communication systems, develop DSP techniques, and lead modeling and verification efforts.

Lead executive compensation governance for a public company: manage annual calendar, prepare Compensation Committee materials and filings, build Excel models for pay decisions and scenario planning, coordinate with Legal/Finance and external advisors, support shareholder engagement, and ensure documented, compliant, scalable compensation processes.

Support the analog design team with circuit implementation for various blocks, assist in design verification, collaborate with different teams, and participate in debugging activities under senior guidance.

The Principal Mixed Signal Design Engineer designs advanced analog ICs, leads design projects, mentors junior engineers, and collaborates across teams for circuit performance validation.

Design and verify mixed-signal CMOS transceiver/SERDES circuits (PLLs, DLLs, ADCs, DACs, TX/RX, CDRs, regulators, amplifiers). Perform SPICE/Spectre/MATLAB-based simulations, optimize for low-power/high-speed, and conduct lab prototype testing to meet performance targets.

Design and verify high-speed analog and mixed-signal circuits (PLL, DLL, ADC, SerDes, CDR, TX/RX, regulators, amplifiers). Perform SPICE/Spectre/MATLAB simulations, post-layout verification, pre-tapeout validation, lab chip bring-up and debugging, and collaborate with layout, verification, and applications teams to deliver analog IP to production.

Oversee daily facility operations across multiple sites, manage preventive maintenance, vendor coordination, and ensure safety compliance, enhancing employee experience.

As a Machine Learning Intern, you will model deep learning algorithms, run performance analysis, and collaborate with Data Scientists on developing Accelerator IPs.

The Senior Staff Engineer will design and validate high-performance RF/Analog circuits, specifically Transimpedance Amplifiers and various analog circuits, collaborating across teams to ensure successful production.

Responsible for the design and validation of FET and BiCMOS circuits for high-speed broadband ICs and optical interface chips. Collaborate on post-silicon validation and transition to mass production.

The Staff Firmware Engineer will design, implement, and optimize SSD firmware features, perform failure analysis, and collaborate across teams to ensure effective firmware development and deployment.

The Sr. Staff Engineer will verify AI/HPC systems, develop test strategies, and create complex verification environments, collaborating on SoC methodologies.

Develop architecture for verification environments, write test plans, develop tests, debug issues, and verify software tools for multi-core SoCs.

As an Analog Layout Staff Engineer, you'll run simulations, collaborate on designs, and lead in the development of precision analog circuits, ensuring projects meet specifications through teamwork and iterative debugging.

Lead verification of AI/HPC SoCs, develop verification architecture using System Verilog and UVM, and analyze designs for test strategies.