Teams at Cadence Design Systems

Leads customer and partner engagements for Cadence timing signoff and closure solutions across advanced semiconductor nodes. Drives STA, IR Drop, power and timing closure benchmarks, flow optimization, tool adoption, and methodology deployment. Collaborates with R&D and product engineering, influences tool enhancements, leads technical programs, and represents Cadence through industry presentations and technical publications. Requires deep advanced-node signoff expertise, scripting skills, customer leadership, and familiarity with Cadence EDA tools.

Develops high-speed wireline communications transceivers through numerical modeling and architecture. Selects and specifies transceiver components, evaluates end-to-end system tradeoffs, collaborates with analog and digital designers, and supports laboratory characterization of completed designs. The role requires advanced mathematical modeling, communication systems, signal processing, coding, data analysis, signal propagation, circuit knowledge, and experimental skills. The position is based full-time in San Jose.

Design and develop analog and mixed-signal IC circuit blocks from architecture and specification through final verification. Contribute to long-reach SerDes designs, including drivers, receivers, serializers, deserializers, PLLs, phase interpolators, clock distribution, ADCs, DACs, bias circuits, bandgaps, and voltage regulators. The role requires expertise in jitter, signal equalization, Cadence simulation tools, post-layout verification, laboratory testing, and high-speed designs at 16 Gbps or greater in 16nm or smaller technologies.