Teams at Cadence Design Systems

Design and develop analog and mixed-signal IC circuit blocks from initial architecture and specification through final verification. The role focuses on long-reach CMOS SerDes, including drivers, receivers, serializers, PLLs, clock distribution, ADCs, DACs, and voltage regulators. Responsibilities include addressing jitter and signal equalization, circuit simulation, post-layout verification, and collaboration with engineering teams. Candidates should have at least five years of CMOS SerDes or high-speed I/O experience and an MS or PhD in electrical engineering.

Leads customer and partner engagements for Cadence timing signoff and closure solutions across advanced semiconductor nodes. Drives STA, IR Drop, power and timing closure benchmarks, flow optimization, tool adoption, and methodology deployment. Collaborates with R&D and product engineering, influences tool enhancements, leads technical programs, and represents Cadence through industry presentations and technical publications. Requires deep advanced-node signoff expertise, scripting skills, customer leadership, and familiarity with Cadence EDA tools.

Develops high-speed wireline communications transceivers through numerical modeling and architecture. Selects and specifies transceiver components, evaluates end-to-end system tradeoffs, collaborates with analog and digital designers, and supports laboratory characterization of completed designs. The role requires advanced mathematical modeling, communication systems, signal processing, coding, data analysis, signal propagation, circuit knowledge, and experimental skills. The position is based full-time in San Jose.