Teams at Blue Origin

Lead end-to-end ASIC/SoC design and verification for TeraWave RFIC/ASICs, from requirements and RTL through FPGA/silicon bring-up. Responsibilities include complex subsystem and SoC verification, DSP/modem design, ARM integration, high-speed interface integration, performance/power optimization, backend support (DFT/STA), formal verification, and post-silicon validation.

Design and develop RFICs and mixed-signal ASICs using Cadence Virtuoso and Spectre RF. Build analog models and verification methodologies, create and execute pre/post-silicon test plans, trade off noise/linearity/power, support lab integration and troubleshooting, resolve layout and timing issues, collaborate with systems/firmware/architecture teams, and adopt AI-based methods across design, simulation, verification, characterization, and manufacturing.

Lead design and development of modem PHY IP for Terawave ASIC and prototypes. Translate algorithms into hardware architectures, build bit-accurate models, perform trade studies, define interfaces, support FPGA/silicon bring-up, collaborate with systems/ASIC/RF/verification teams, and analyze simulation/emulation/lab/silicon data to improve PHY performance and validation.