Teams at Axelera AI

Lead ASIC physical design activities from RTL to GDS including synthesis, floorplanning, place-and-route, CTS, timing optimization, extraction, physical verification, EMIR signoff, and IP integration. Drive automation with Python/Tcl/Bash, debug physical-design challenges, and collaborate closely with architecture, RTL, and verification teams to deliver multi-core in-memory compute SoCs.

Design and implement digital micro-architectures and RTL for AI SoC components, integrate 3rd-party IPs, run static checks and verification, optimize for performance/power/area, automate flows with scripting, and collaborate with verification and physical design teams on DFM/DFT and timing closure.

Own platform-level architecture for datacenter AI accelerator systems from server to rack to datacenter. Translate compute, memory, and interconnect requirements into hardware specs; define interconnects, PCIe/CXL integration, power budgeting, RAS/operability, and scalability. Collaborate with silicon, software, AIIS, partners and customers to align architecture and drive platform design best practices.