Teams at Astera Labs

Lead cross-functional execution of complex ASIC/SoC programs from concept through tapeout. Own program plans, schedules, risk registers, status reporting, and phase-gate execution. Coordinate architecture, RTL, verification, DFT, physical design, CAD/EDA, IP, foundry and vendor dependencies. Drive risk mitigation, decision forums, and scalable program practices; partner with post-silicon validation for issue resolution.

Senior Design Verification Engineer responsible for developing and executing UVM/SystemVerilog verification environments, integrating C/C++ via DPI/PLI, creating constrained-random tests, writing assertions and coverage, using third-party VIPs (PCIe, Ethernet, NVMe, DDR, etc.), automating infrastructure with scripting, and collaborating with RTL designers to debug SoC silicon for server, storage, and networking applications.

Lead design verification for complex SoC/silicon products using UVM and C/C++-based environments. Develop UVM testplans, constrained-random stimuli, assertions and coverage, integrate C/C++ via DPI/PLI, automate infrastructure with scripting, use 3rd-party VIPs (PCIe, Ethernet, InfiniBand, DDR, NVMe, USB), and collaborate with RTL designers to debug in simulation, co-simulation, and emulation.