Teams at Astera Labs

Lead cross-functional execution of complex ASIC/SoC programs from concept through tapeout. Own program plans, schedules, risk registers, status reporting, and phase-gate execution. Coordinate architecture, RTL, verification, DFT, physical design, CAD/EDA, IP, foundry and vendor dependencies. Drive risk mitigation, decision forums, and scalable program practices; partner with post-silicon validation for issue resolution.

Lead end-to-end static timing analysis (STA) and timing closure for complex connectivity SoCs from RTL through sign-off. Develop/validate SDC/MMMC constraints, define I/O timing budgets, run multi-corner/multi-mode STA, apply sign-off methodologies at TSMC 7nm+, generate timing ECOs, and collaborate with RTL, physical design, verification, and IP teams to ensure full-chip timing convergence.

The Physical Design Manager will lead a team to implement connectivity ASICs, handling execution from RTL to GDSII, while ensuring design quality and mentoring engineers.