Teams at Astera Labs

The Technical Lead will design high-performance digital solutions, manage IP integration, ensure timing closure, and utilize design tools for connectivity solutions.

The Physical Design Manager will lead a team to implement connectivity ASICs, handling execution from RTL to GDSII, while ensuring design quality and mentoring engineers.

The role involves designing and verifying advanced node CMOS mixed-signal circuits, including PLLs, ADCs, and other analog components, while collaborating with global teams.