Teams at Astera Labs

Lead architecture and production delivery of embedded firmware and software for Ethernet retimers and high-speed connectivity platforms. Own hardware abstraction, drivers, calibration, link management, diagnostics, telemetry, validation, and customer deployment. Debug PHY, SERDES, FEC/PCS, MAC, and retimer interactions using lab measurements and automation. Provide technical leadership across silicon, analog, systems, validation, and applications teams while mentoring engineers and supporting customer bring-up.

Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, data conversion, references, and regulators. Lead designs from architecture through schematic, layout supervision, verification, silicon bring-up, characterization, and debug. Define test plans, collaborate across engineering functions, establish design standards, conduct technical reviews, and mentor engineers. Support advanced FinFET designs with focus on power, area, performance, signal integrity, and production tape-out.

Leads DFT architecture and execution for high-speed PCIe and Ethernet signal-conditioning products. Defines test, coverage, observability, diagnostics, scan, ATPG, MBIST, LBIST, JTAG, and SerDes BIST strategies across advanced multi-die designs. Partners with design, verification, packaging, manufacturing, and test teams through tape-out, silicon bring-up, yield analysis, and production ramp. Mentors engineers, coordinates cross-functional execution, and works with OSATs and ATE vendors to improve quality, manufacturability, and production readiness.