Teams at Astera Labs

Develop and maintain UVM-based verification environments for complex connectivity silicon. Create verification plans, constrained-random tests, assertions, coverage models, VIP integrations, and automated regression infrastructure. Debug simulation, co-simulation, and FPGA emulation failures while collaborating with RTL designers. Verify protocols including PCIe, Ethernet, InfiniBand, DDR, NVMe, and USB, and contribute to technical reviews and verification closure.

Design and integrate high-performance connectivity silicon for AI infrastructure, including PCIe and Ethernet controllers, bridges, switches, and SerDes-related IP. Responsibilities span microarchitecture, SystemVerilog or Verilog RTL, synthesis, timing closure, IP integration, DFT, clock-domain crossing, simulation, emulation, and full-chip implementation through GDS handoff. Collaborate with verification, physical design, firmware, and system teams while automating workflows with Python or Perl.

Lead end-to-end static timing analysis (STA) and timing closure for complex connectivity SoCs from RTL through sign-off. Develop/validate SDC/MMMC constraints, define I/O timing budgets, run multi-corner/multi-mode STA, apply sign-off methodologies at TSMC 7nm+, generate timing ECOs, and collaborate with RTL, physical design, verification, and IP teams to ensure full-chip timing convergence.