Jobs at Astera Labs

Lead cross-functional execution of complex ASIC/SoC programs from concept through tapeout. Own program plans, schedules, risk registers, status reporting, and phase-gate execution. Coordinate architecture, RTL, verification, DFT, physical design, CAD/EDA, IP, foundry and vendor dependencies. Drive risk mitigation, decision forums, and scalable program practices; partner with post-silicon validation for issue resolution.

Senior Design Verification Engineer responsible for developing and executing UVM/SystemVerilog verification environments, integrating C/C++ via DPI/PLI, creating constrained-random tests, writing assertions and coverage, using third-party VIPs (PCIe, Ethernet, NVMe, DDR, etc.), automating infrastructure with scripting, and collaborating with RTL designers to debug SoC silicon for server, storage, and networking applications.

Lead design verification for complex SoC/silicon products using UVM and C/C++-based environments. Develop UVM testplans, constrained-random stimuli, assertions and coverage, integrate C/C++ via DPI/PLI, automate infrastructure with scripting, use 3rd-party VIPs (PCIe, Ethernet, InfiniBand, DDR, NVMe, USB), and collaborate with RTL designers to debug in simulation, co-simulation, and emulation.

Lead end-to-end static timing analysis (STA) and timing closure for complex connectivity SoCs from RTL through sign-off. Develop/validate SDC/MMMC constraints, define I/O timing budgets, run multi-corner/multi-mode STA, apply sign-off methodologies at TSMC 7nm+, generate timing ECOs, and collaborate with RTL, physical design, verification, and IP teams to ensure full-chip timing convergence.

The Physical Design Manager will lead a team to implement connectivity ASICs, handling execution from RTL to GDSII, while ensuring design quality and mentoring engineers.

Develop and maintain embedded C/C++ firmware for analog and Ethernet connectivity devices, perform low-level hardware bring-up and debugging, write Python test automation, collaborate on validation and CI tooling, participate in code reviews and project tracking, and characterize firmware behavior across operating conditions.