Jobs at Astera Labs

Lead architecture and production delivery of embedded firmware and software for Ethernet retimers and high-speed connectivity platforms. Own hardware abstraction, drivers, calibration, link management, diagnostics, telemetry, validation, and customer deployment. Debug PHY, SERDES, FEC/PCS, MAC, and retimer interactions using lab measurements and automation. Provide technical leadership across silicon, analog, systems, validation, and applications teams while mentoring engineers and supporting customer bring-up.

Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, data conversion, references, and regulators. Lead designs from architecture through schematic, layout supervision, verification, silicon bring-up, characterization, and debug. Define test plans, collaborate across engineering functions, establish design standards, conduct technical reviews, and mentor engineers. Support advanced FinFET designs with focus on power, area, performance, signal integrity, and production tape-out.

Leads DFT architecture and execution for high-speed PCIe and Ethernet signal-conditioning products. Defines test, coverage, observability, diagnostics, scan, ATPG, MBIST, LBIST, JTAG, and SerDes BIST strategies across advanced multi-die designs. Partners with design, verification, packaging, manufacturing, and test teams through tape-out, silicon bring-up, yield analysis, and production ramp. Mentors engineers, coordinates cross-functional execution, and works with OSATs and ATE vendors to improve quality, manufacturability, and production readiness.

Develop and maintain UVM-based verification environments for complex connectivity silicon. Create verification plans, constrained-random tests, assertions, coverage models, VIP integrations, and automated regression infrastructure. Debug simulation, co-simulation, and FPGA emulation failures while collaborating with RTL designers. Verify protocols including PCIe, Ethernet, InfiniBand, DDR, NVMe, and USB, and contribute to technical reviews and verification closure.

Design and integrate high-performance connectivity silicon for AI infrastructure, including PCIe and Ethernet controllers, bridges, switches, and SerDes-related IP. Responsibilities span microarchitecture, SystemVerilog or Verilog RTL, synthesis, timing closure, IP integration, DFT, clock-domain crossing, simulation, emulation, and full-chip implementation through GDS handoff. Collaborate with verification, physical design, firmware, and system teams while automating workflows with Python or Perl.

Lead end-to-end static timing analysis (STA) and timing closure for complex connectivity SoCs from RTL through sign-off. Develop/validate SDC/MMMC constraints, define I/O timing budgets, run multi-corner/multi-mode STA, apply sign-off methodologies at TSMC 7nm+, generate timing ECOs, and collaborate with RTL, physical design, verification, and IP teams to ensure full-chip timing convergence.

Lead cross-functional execution of complex ASIC/SoC programs from concept through tapeout. Own program plans, schedules, risk registers, status reporting, and phase-gate execution. Coordinate architecture, RTL, verification, DFT, physical design, CAD/EDA, IP, foundry and vendor dependencies. Drive risk mitigation, decision forums, and scalable program practices; partner with post-silicon validation for issue resolution.