Jobs at Arm

Senior PCIe Verification Engineer responsible for creating and executing verification plans and testbenches for PCIe IP/SoC, debugging designs, collaborating with RTL designers and validation teams, and ensuring protocol compliance and quality.

Design and integrate PCIe, CXL, UCIe and other I/O subsystems into SoCs. Write micro-architecture specs, develop RTL in Verilog, run static checks, debug builds, collaborate with verification, performance, and backend teams, and mentor others to deliver complex SoC projects.

Verify PCIe/CXL high-speed IOs at subsystem level: create verification strategies and test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation and emulation, analyze performance and interoperability, debug issues, improve methodologies, and mentor junior engineers while collaborating with architects and project management.

Design and integrate PCIe, CXL and other subsystems for SoCs: write micro-architecture specs, develop RTL in Verilog, debug, run static checks, collaborate with verification, performance analysis and backend teams, and mentor team members.

Manage operational workflows, coordinate team activities, and ensure accountability within Engineering functions, while supporting cross-functional communication.

Support deployment, training, and support of internal SoC design and verification flows. Work with project engineers and methodology developers to ensure front-end and back-end flows function correctly, ramp teams, liaise with EDA vendors to resolve tooling issues, and identify efficiency improvements across engineering projects.

Lead daily site operations for a new Seattle office, managing vendors, budgets, facilities maintenance, health & safety, workplace ticketing, events, and stakeholder engagement to deliver a high-quality employee experience.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define system-level interconnect strategies (topology, QoS, latency, bandwidth, power), collaborate across CPU/GPU/NPU/memory teams, drive standards adoption, own performance modeling and RTL/verification strategy, lead debug/root-cause analysis, mentor engineers, and shape roadmaps for next-generation interconnect IP to support tape-out and silicon validation.

The engineer will verify PCIe and CXL subsystems, collaborate on testplans, develop UVM testbenches, and improve verification methodologies.