Jobs at Arm

The engineer will verify PCIe and CXL subsystems, collaborate on testplans, develop UVM testbenches, and improve verification methodologies.

Develop and improve front-end ASIC/SoC build methodologies, CAD flows, and automation from RTL development through implementation handoff. Build production-quality infrastructure for RTL quality, verification, IP management, regression, and release readiness. Collaborate with engineering teams and EDA vendors to resolve bottlenecks, evaluate AI and automation technologies, and drive methodology adoption across projects.

Support deployment, training, and support of internal SoC design and verification flows. Work with project engineers and methodology developers to ensure front-end and back-end flows function correctly, ramp teams, liaise with EDA vendors to resolve tooling issues, and identify efficiency improvements across engineering projects.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define system-level interconnect strategies (topology, QoS, latency, bandwidth, power), collaborate across CPU/GPU/NPU/memory teams, drive standards adoption, own performance modeling and RTL/verification strategy, lead debug/root-cause analysis, mentor engineers, and shape roadmaps for next-generation interconnect IP to support tape-out and silicon validation.

Support engineering organizations with workforce planning, headcount forecasting, staffing coordination, capacity tracking, operational reporting, running key cadences, and improving processes to align resources with business priorities.

Design and architect Security IP and SoC security subsystems. Develop RTL, constraints, and specifications; drive design exploration, optimization, and bug fixes. Collaborate with verification and implementation for test plans, verification closure, debug, and sign-off. Mentor team members and support project management, roadmaps, and processes.

Lead a global team to define and deliver SoC-level clock, reset, power and thermal architectures. Manage requirements, prototypes, verified designs, cross-functional partners and post-silicon bring-up to produce power-efficient SoC products. Drive solutions for DVFS, power gating, voltage regulation, digital clocking, resets, and standards compliance.

Design and define SoC security architectures including Root of Trust, Secure Boot, key management, confidential compute, attestation, secure manufacturing, and device lifetime management. Perform threat modeling, cryptographic and side-channel analysis, define software security requirements, and lead cross-functional teams to implement hardware/software access control, isolation, and security policies.

Design and deploy scalable synthesis methodologies and automation for Arm-based SoC implementation. Improve and support synthesis flows (including SIMPL), resolve PPA bottlenecks, enable front-end teams, and ensure successful deployment of low-power and DFT insertion techniques across advanced technodes.

Senior PCIe Verification Engineer responsible for creating and executing verification plans and testbenches for PCIe IP/SoC, debugging designs, collaborating with RTL designers and validation teams, and ensuring protocol compliance and quality.

Design and integrate PCIe, CXL, UCIe and other I/O subsystems into SoCs. Write micro-architecture specs, develop RTL in Verilog, run static checks, debug builds, collaborate with verification, performance, and backend teams, and mentor others to deliver complex SoC projects.

Verify PCIe/CXL high-speed IOs at subsystem level: create verification strategies and test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation and emulation, analyze performance and interoperability, debug issues, improve methodologies, and mentor junior engineers while collaborating with architects and project management.

Design and integrate PCIe, CXL and other subsystems for SoCs: write micro-architecture specs, develop RTL in Verilog, debug, run static checks, collaborate with verification, performance analysis and backend teams, and mentor team members.