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Intel Corporation

Senior Staff STA / Structural / Physical Design Engineer

Posted 5 Days Ago
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2 Locations
Senior level
2 Locations
Senior level
As a Senior Staff Structural Design Engineer, you will lead a team in static timing analysis and performance verification for high-speed PHY designs. You'll collaborate with architecture and design teams, drive timing closure using industry tools, and mentor junior engineers, ensuring designs meet timing signoff requirements while managing complex I/O budgets.
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Job Details:

Job Description: 

ISCP MIP MYS is seeking Senior Staff STA for the role of Structural Design Engineer to join our talented and vibrant team. You will be directly involved in delivering next-generation high speed PHY designs for SoC applications on Ieading process node
Key Responsibilities for this position include but not limited to:

  • Lead and Manage a group of Static Timing Analysis (STA) engineers/Performance Verification (PV) engineers

  • Working closely with Architecture and Design team to understand, define and generate timing specification/clocking/constraints/extractions/ptpx

  • Drive Implementation requirements (for example, Clock Tree Synthesis targets), Influence and Continuous seek to improve the Timing Closure methodology, etc

  • Drive timing closure, execute STA using industry tool (Primetime) and perform various quality check to ensure design converges on the timing signoff requirements.

  • Analyze timing report and proficient in using script to debug, automate tasks and provide timely feedback for timing ECO.

  • Define and develop I/O budgets and drive for IP budget convergence.

Qualifications:

You should possess a relevant educational qualification, BSEE or equivalent with 8+ years/MSEE or equivalent with 6+ years design experience in the structural/physical design domain. Additional qualifications include:

  • Have multiple tape-out experience in deep submicron process nodes

  • Must have in depth, extensive knowledge and hands-on experience in Static timing analysis and timing signoff, including SDC development and timing budgeting.

  • Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage

  • Experienced in industry STA tools: Primetime and Primetime SI

  • Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL and Verilog.

  • Experience of mentoring junior team members and charting their development for success.

  • Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

          

Job Type:Experienced Hire

Shift:Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations:Malaysia, Kulim

Business group:The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Top Skills

Perl
Tcl
Verilog
Vhdl

Intel Corporation Toronto, Ontario, CAN Office

150 Bloor St W, Toronto, ON, Canada, M5S 2X9

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