About Altera
Altera is at the forefront of hardware acceleration, building innovative solutions for next-generation systems. We are seeking a highly skilled Engineer to join our team. This role is critical in advancing our high-level synthesis (HLS) compiler stack.
Responsibilities
Create example designs for offloading compute to FPGA fabric using HLS IP cores and Open FPGA Stack
This is a 4-month contract position
Salary
Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge.
Estimated Salary Range: $88,300 - $127,000 CAD
We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.
Required Qualifications
3+ years of experience with Open FPGA Stack, Sycl and OneAPI
3+ years of experience in C++ (modern standards), with a strong software engineering foundation.
2+ years of experience in compiler design, optimization techniques, and code generation.
2+ years of experience with parallelism, pipelining, and hardware resource optimization in compilers.
Preferred Qualifications
Contributions to MLIR or Clang open-source projects.
Experience with Verilog/VHDL or other hardware description languages.
Knowledge of high-level hardware programming models (e.g., SYCL, OpenCL, CUDA).
Familiarity with FPGA or ASIC design flows.
Strong communication skills and experience working in cross-functional teams.
Required Qualifications
3+ years of experience with Open FPGA Stack, Sycl and OneAPI
3+ years of experience in C++ (modern standards), with a strong software engineering foundation.
2+ years of experience in compiler design, optimization techniques, and code generation.
2+ years of experience with parallelism, pipelining, and hardware resource optimization in compilers.
Preferred Qualifications
Contributions to MLIR or Clang open-source projects.
Experience with Verilog/VHDL or other hardware description languages.
Knowledge of high-level hardware programming models (e.g., SYCL, OpenCL, CUDA).
Familiarity with FPGA or ASIC design flows.
Strong communication skills and experience working in cross-functional teams.
Applicants must be eligible to obtain any necessary U.S. export authorizations.
Job Type: Contract Employee (Fixed Term)Shift:Shift 1 (Canada)Primary Location:Toronto, Ontario, CanadaAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Top Skills
Altera (altera.com) Toronto, Ontario, CAN Office
151 Bloor St W, Toronto, Ontario, Canada, M5S 1S4
