Jobs at Positron AI

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.

Own synthesis, timing closure, constraint development, and implementation readiness for ASIC accelerator partitions. Execute Cadence Genus or Synopsys Design Compiler flows, develop SDC and MMMC environments, optimize timing, area, power, and congestion, and collaborate with RTL, verification, DFT, physical design, and backend teams. Improve synthesis methodology, analyze QoR and timing bottlenecks, support vendor partners, and apply AI tools to engineering automation and report analysis.

Lead physical implementation of AI accelerator ASICs from floorplanning through tapeout. Drive placement, CTS, P&R, signal/IR/EM closure, signoff, and methodology development. Partner with RTL, synthesis, DFT, package, and backend teams to deliver timing, power, area, congestion, and yield targets, and apply AI techniques to optimize QoR.

Design and verify synthesizable SystemVerilog RTL for AI inference ASIC and SoC IP blocks. Responsibilities include microarchitecture support, RTL implementation, assertions, lint, CDC/RDC, synthesis, timing, PPA optimization, interface integration, scripting, verification collaboration, and post-silicon debugging. The role offers mentorship and growth toward greater technical ownership.

Leads microarchitecture, RTL implementation, and signoff for complex IP blocks and subsystems in AI inference ASICs and SoCs. Owns PPA optimization, interface and memory integration, lint, CDC/RDC, DFT, synthesis, and timing closure. Collaborates with architecture, verification, physical design, and vendors; develops design methodologies and automation; supports silicon bring-up and customer engagements; and mentors junior engineers while driving technical decisions.

Own end-to-end DFT architecture and implementation for AI accelerator ASICs, including scan, compression, ATPG, MBIST, boundary scan, IJTAG, verification, and physical-design integration. Drive pre-silicon coverage, timing and power-aware test implementation, silicon bring-up, and cross-functional execution through tapeout. The role requires hands-on RTL, synthesis, gate-level verification, Tessent tool expertise, scripting, and failure analysis across multiple production tapeouts.

Contribute to physical implementation of AI accelerator ASICs from floorplanning and macro placement through tapeout. Responsibilities include clock tree synthesis, place and route, timing, power, signal integrity, IR/EM, DRC, LVS, congestion, ECOs, metal fill, and signoff closure. The role also supports implementation methodology, advanced-node tapeouts, AI-enabled QoR analysis, and collaboration with RTL, synthesis, DFT, package, and backend teams.

Lead architecture and performance exploration for next-generation AI inference accelerators. Build analytical models and simulation frameworks, define subsystem interfaces and roadmaps, and drive hardware/software co-design with compiler, runtime, ML, and silicon teams to optimize latency, throughput, memory, interconnects, power, and cost for evolving LLMs and transformer-based workloads.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.