As a Senior Mask Layout Design Engineer at NVIDIA, you'll collaborate with various engineering teams to perform physical layouts for mixed-signal functions in sub-micron CMOS technologies, utilizing Cadence tools. Your responsibilities include floor planning, custom layout, design rule verification, and interacting with foundries, as well as debugging and customizing DRC and LVS flows.

The Senior Signal and Power Integrity Engineer will design high-frequency channels, create layout guidelines, simulate components, and conduct lab measurements. They will master technology related to InfiniBand, Ethernet, and PCI-Ex while working closely with engineering teams.

As a Technical Product Specialist at NVIDIA, you will test and provide feedback on Digital Human Tech products, develop tools using Python/C++, and enhance customer communication with the engineering team. Your role includes deploying microservices, reporting results, and creating documentation to drive customer success.

The Senior Memory Controller Verification Engineer will define verification scope, develop test infrastructures, collaborate with design teams, ensure code coverage, and assist with post-silicon debug. The role involves working on memory controller designs and verification methodologies.

The Performance Engineering Intern will run performance tests on PC games and benchmark applications, build automation scripts, design tools for performance analysis, configure computer systems, and analyze test results to generate reports.

As a Digital Design Manager, you will lead a team in developing mixed-signal chips, supervise planning and specification of algorithms, guide digital circuit design, ensure verification of designs, and drive chip tape-outs and performance optimization, while collaborating with multi-functional teams.

As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design of GPUs and ASICs, implement advanced verification methodologies, and collaborate with various teams to ensure design accuracy. You will develop verification infrastructure and contribute to product lines affecting multiple sectors.