The Principal Design Engineer at Cadence will lead the digital design process for High Speed Serdes, collaborating with technical staff on project development. Responsibilities include defining digital microarchitecture, RTL logic design, debugging, and functional verification, as well as understanding digital architecture, timing constraints, and wireline standards.

The Lead C++ Software Engineer will develop and enhance algorithms for the Protium FPGA-Based Prototyping product. Responsibilities include enhancing Static Timing Analysis, optimizing runtime and memory, developing EDA automation flows, and writing design specifications and unit tests.

The Senior Principal Verification Engineer will lead a team in the verification of digital RTL, develop reusable verification components, and manage verification plans using Cadence tools. Responsibilities include project planning, architecture of verification environments, developing UVM-SV scoreboards, and collaborating closely with design teams.

As a Software Intern at Cadence, you will engage in R&D focused on improving simulation and characterization of advanced circuits. Responsibilities include developing machine learning technologies, enabling parallelization for characterization runs, and creating infrastructure for data mining in circuit characterization.

The Lead Digital Verification Engineer will develop high-performance physical IP for protocols, contributing to digital verification tasks like flow development, test planning, and coverage closure. The role requires collaboration with engineers and project managers, along with independent task completion. Experience in digital verification methodologies and scripting languages is essential.